Timing Recovery using group delay compensation

ABSTRACT

An electronic transmit/receive device employs an equalized envelope derived timing system to compensate for differential time delay occurring at upper and lower bandedges of the received signal. The received signal is split into a complex signal and the envelope derived timing system is utilized to perform amplitude and delay distortion compensation on the received signal. The amplitude and delay distortion compensation is performed by employing bandedge filters which preferably take the form of Finite Impulse Response (FIR) filters.

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BACKGROUND OF THE INVENTION

The present invention relates generally to electronic communication systems and, more particularly, to a system for timing recovery in a receiver. A receiver accepts a transmission signal sent to it by a remote transmitter over a transmission medium, such as, for example, a telephone cable, microwave link, or other "channel." Such media introduce distortion, noise and other impairments into the received signal, which can cause the receiver to make decoding errors, such that the receiver does not receive an exact duplicate of the message, or symbols, being transmitted.

A transmitter, such as found in a modem, typically parses a message into groups of bits, and encodes each of these groups of bits into symbols, thus creating a sequence of symbols from a sequence of bits. These symbols are complex numbers of the form a +j*b, where j is the square root of the value (-1). The full set of allowed complex numbers for a given modulation system of a transmitter is known as the system's signal constellation. The encoding process is performed at a periodic rate, called the symbol rate. Once generated, the symbols are filtered by the transmitter to control signalling bandwidth, and then modulated by a carrier wave, which creates a signal that is suitable for transmission over a communication channel.

The exact symbol rate of a transmitter is typically under the control of a local time reference, such as a crystal oscillator. While, it is possible to communicate this timing information explicitly, the system constraints of most transmitters are usually such that it is undesireable to invest either signalling bandwidth or increase signal power for this purpose. Therefore, the discrete amplitude and phase changes imposed on the carrier wave are actually used to convey two things to the receiver: the data sequence, and the timing information necessary to decode this sequence at the receiver.

A receiver, such as found in a modem, is designed to estimate the transmitted sequence with the minimum number of errors possible. Ideally, the receiver's local timing reference will be identical to that of the remote transmitter, in both frequency and phase. However, modems for data communication over the telephone network can have local clock references that vary as much as +/-200 parts per million (ppm) between remote transmitter and local receiver. Thus, because of such discrepancies, the receiver must extract information from the incoming signal in order to estimate the frequency and phase of the clock associated with the incoming signal, so that the incoming signal may be sampled at the optimum times.

A common method used for recovering timing from such a waveform is called Envelope Derived Timing (EDT), which is based on the phenomena that periodic changes in phase and amplitude in the carrier waveform cause changes in the carrier's power envelope. A receiver utilizing EDT can reconstruct the symbol rate clock from the variations in the power envelope detected by the receiver.

A carrier waveform modulated by the transmitter in the manner described above will occupy a frequency spectrum that is centered around the carrier frequency and at least as wide as the symbol rate, plus some excess bandwidth. The portion of this spectrum that is associated with the power envelope are the regions centered at the carrier frequency plus one-half the symbol rate and the carrier frequency minus one-half the symbol rate. These two frequency regions are generally known as the band edges.

Unfortunately, the power envelope of a signal can be adversely affected by channel impairments, particularly amplitude and phase distortion at the band edges. To compensate for such impairments, many receiver designs include an adaptive equalizer which compensates for amplitude and phase distortion on the transmission channel in the data recovery path. Such equalizers depend on accurate timing recovery in order to function properly. For example, some systems have sometimes used a straightforward timing loop configuration, without compensating for amplitude or delay distortion of the transmitted message. With careful tuning of the receiver, this approach may prove adequate for slower transmissions with, for example, a transmitted symbol rate of 2400 symbols per second ("s/s"). See the standards adopted by the International Telecommunications Union--Telecommunications Standardization Sector ("ITU-T") up through v.32bis. However, faster transmission rates may require better techniques for recovering timing information.

Typically, a receiver reconstructs the timing envelope from energy near the upper and lower bandedges of the signal. Often, the wider the bandwidth used, the more distortion that is introduced into the signal by, for example, the transmission channel. Indeed, the requirements of ITU-T Standard v.34, which describes symbol rates as high as 3429 s/s, pushes the signal bandedges (where useful timing information is located) into severely distorted regions of telephone channels.

In such frequency regions, there is substantial rolloff (reduced signal strength) induced by the telephone transmission line. Further, these frequency regions may be subjected to considerable delay distortion. This type of distortion, which is related to the rate of change of phase with respect to frequency, causes signal energy in one band edge to arrive at the receiver at a different time than energy from the other bandedge. The timing envelope is most robust when the energy from the upper and lower sidebands arrives at the timing envelope detector simultaneously, and is degraded otherwise. For example, if the delay characteristic of a given channel is 5 milliseconds at the lower bandedge and 2 millisceconds at the upper bandedge, then if the transmitter simultaneously sends a burst of energy at both bandedges, the upper bandedge portion of this energy will arrive 3 ms. before the lower bandedge energy. If the transmitted burst is of 5 ms. duration, then there will be a strong envelope for 2 ms., but if the burst is of 2 ms. duration, there is no real timing information available to the receiver. The data sent by the transmitter is intentionally randomized in order to achieve certain spectral characteristics. Since timing energy is implicit in the phase and amplitude of the carrier wave, some data patterns (ie., those with dramatic changes) produce a strong timing signature while others do not. Short sequences rich in timing information patterns are more likely than long ones. Therefore, in order for the receiver to extract as much timing information as possible, it is important not to waste shorter patterns bursts, such as those of less than 3 ms. in the example above. These short patterns are wasted in a system that does not have timing equalization.

The timing recovery system in a modem's receiver is often the limiting factor in achieving high transmission speeds on a telephone channel. The rest of the modem receiver's systems, such as, for example, equalizers, carrier tracking loops, and echo cancelers, are often capable of operating at higher data rates than the timing recovery system. In order to maintain high symbol rate transmission, some have simply tried not to operate on channels with severely limited transmission characteristics, or, alternatively, have used complex techniques of questionable stability.

SUMMARY OF THE INVENTION

Applicants have noted that, on certain channels with severe delay distortion at higher or lower frequencies, a major limitation to higher symbol rate transmission is often the relative delay distortion of the modem signal at the bandedges. Thus, in a principal aspect, the present invention relates to an envelope derived timing system in a data receiver.

The system receives a signal that has been modulated by changing the amplitude and phase of the carrier at discrete periodic intervals. The signal is sampled and digitized by an Analog to Digital Converter at a sample rate that is high enough to preserve the information content of the incoming signal. The signal may be used by, for example, an equalizer and decoder, to obtain a data signal.

The system includes a timing interpolator and a timing loop interconnected to the timing interpolator. The timing loop includes a timing compensator which receives the sampled signal and delays upper and lower bandedge energy to compensate for delay distortion at the upper and lower bandedges. The timing compensator provides time-compensated component signals. A timing recovery system processes the time-compensated component signals and responsively provides a phase control signal to the interpolator.

Thus, an object of the present invention is improved envelope derived timing recovery in an electronic data transmission system. Another object is a timing recovery system that more reliably allows the transmission of data at a higher rate. Still another object is a timing recovery system that operates more reliably with transmission lines that introduce impairments into a transmitted signal. These and other objects, features, and advantages of the present invention are discussed or apparent in the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The preferred embodiment of the present invention is described herein with reference to the drawings wherein:

FIG. 1 is a block diagram of an electronic data transmission system utilizing the present invention;

FIG. 2 is a block diagram of the transmitter shown in FIG. 1;

FIG. 3 is a graph illustrating a simple four-point mapping system that may be utilized by the transmitter shown in FIG. 2;

FIG. 4 is a block diagram of the receiver shown in FIG. 1;

FIG. 5 is a block diagram of the envelope derived timing system shown in FIG. 4;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIGS. 1-6, the present invention is shown as an equalized envelope derived timing system. The system is utilized in an electronic data transmission system 22. See FIG. 1. The transmission system 22 is shown in FIG. 1 for purposes of illustration only, since a great variety of such systems exist. The transmission system 22 includes two sources of information, such as exemplary computers 24, 26, and two transmit/receive devices, such as exemplary modems 28, 30, that are interconnected via a communication medium 32. The transmit/receive devices may, of course, be within, or a part of, the sources of information. The modems each include a transmitter 34, 36 for sending data along the medium, and a receiver 38, 40 for receiving the transmitted signal from the medium. As shown in FIG. 2, a transmitter may include a scrambler 202, encoder or mapper 204, filter 206, a complex multiplication operation 208 to shift the center frequency of the filtered symbols, and digital to analog converter 212. There are, of course, many different receiver and transmitter architectures. The structure shown in the drawings are for illustration purposes only. Preferably a modem such as seen in FIGS. 1-6 may be implemented by a microprocessor operating under stored program control. Such modems include a Read-Only Memory (ROM) for storage of control programs and permanent data and Random Access Memory (RAM) for temporary storage of programs and data. Input/Output (I/O) circuitry is incorporated either in the microprocessor or in peripheral chips for receiving and transmitting information to and from the microprocessor.

The data transmission device shown in FIG. 2 first randomizes, or scrambles data received from the computer. This operation insures the presence of timing energy in the subsequent transmit waveform. The data is advantageously randomized by the scrambler prior to any other processing in order to guarantee sufficient timing energy in the transmit signal.

Next, the encoder/mapper maps and encodes data bits received from the scrambler into symbols at the rate of once per symbol period. FIG. 3 shows a simple four-point mapping system for 4800 bits per second ("bps") from ITU-T standard v.32 for 4800 bits per second transmission. In the simple illustrative example shown in FIG. 3, each pair of bits is mapped to one of four points. This data-to-symbol mapping may, in different systems, take one of the following forms: amplitude modulation, amplitude and phase modulation, generally known as Quadrature Amplitude Modulation (QAM), a combination of forward error correction and QAM called Trellis Coded Modulation (TCM), or one of various other techniques.

The resulting sequence of symbols is then processed by the filter 206 and summing point 208 to generate a complex signal 210. The real part of the complex signal is then converted at 212 to an analog waveform by the converter and transmitted via the communications channel to the other modem. The transmitting modem may be considered remote to the modem receiving the information.

The resulting transmit waveform passes through the communications channel and is processed by the receiver. The receiving device must, among other things, recover symbol timing in order to optimally decode the symbol stream, and thus recover the transmitted data. This is often done with a well-known technique called Envelope Derived Timing ("EDT").

A description of conventional timing recovery concepts can be found in The Theory and Practice of Modem Design, by John A. C. Bingham, Chapter 7, or Digital Communication, by Edward A. Lee and David G. Messerschmitt, Chapter 15. A description of interpolator based timing recovery can be found in Floyd M. Gardner's article: Interpolation in Digital Modems--Part 1: Fundamentals, IEEE Transactions on Communications, Vol. 41, No. 3, March 1993, or Part 2: Implementation and Performance, Vol 41, No. 6, June 1993.

The exemplary receiver shown in FIG. 4 includes input, interpolation, and equalization stages as seen at 402, 404 and 406 respectively. The input stage 402 includes a filter 408, summing point 410, and Automatic Gain Control ("AGC") 412. Initial processing of the received transmitted signal 401 is done at the input stage to prepare the signal for further processing.

The input to this first stage is asssumed to be a sequence of discreet time samples represented as digital words that are output from an Analog-to-Digital-Converter (not shown). The noise filter 408 performs several functions, such as filtering of noise added during transmission over the communication channel. The noise filter 408 can also be designed to eliminate D.C. offset imperfections inherent in Analog-to-Digital-Converters often used in modem receivers, as well as power line and power supply noise terms at harmonics of 60 Hz that are introduced by analog electronic components of the modem or terminal equipment. The summing node 410 subtracts an estimate of the local transmitter's echo from the receiver's input path. This is a necessary part of any full duplex modem that utilizes the same band of frequencies for transmission in both directions. The input signal to the Automatic gain Control (AGC) 412 varies in amplitude by 40 dB. or more, depending on the characteristics of the communications channel. The output of the AGC compensates for this uncertainty in receive signal level and furnishes a signal of known constant amplitude to the second stage described below. The second stage includes a phase splitter, timing interpolator, and the Timing Recovery Control Process 418. The phase splitter 414 converts the real signal generated by AGC 412 to its complex components (represented in the drawings by double lines). Such complex components may be represented in the form x+j*y , where x and y are a pair of orthogonal axes that form a two-dimensional space.

The demodulation element 417 shifts the center frequency of the complex signal from the phase splitter 414, which is still centered at the approximately the transmitter's carrier frequency, to approximately zero. This demodulation process is the counterpart of the modulation process 208 in the transmitter block diagram, FIG. 2. The reason that the demodulated signal's center frequency is only approximately zero is because the local time reference that generates the demodulation waveform exp{j*Wc N/T} is, in general, not exactly equal to that of the remote transmitter, and also because the communications channel may introduce frequency shift of several Hertz. This frequency shift is not significant to the operation of the timing recovery system, which is concerned with the difference in upper and lower sideband frequencies, not in the absolute frequencies of the upper and lower sidebands.

The interpolator 416 converts the signal from the demodulation process, which typically is at a sample rate of three samples per symbol, referenced to the local transmitter's symbol rate, to a signal with a sample rate of two samples per symbol, but referenced to the symbol rate of the remote transmitter, which may be significantly different that the local transmitter's symbol rate, as described in the Background of the Invention section. The estimate of the frequency and phase of the remote transmitter is of course produced by the timing recovery system in the local receiver. Under ideal conditions, the local receiver's symbol rate frequency and phase would be precisely equal to that of the remote transmitter, and the channel would not introduce impairments that would make timing recovery problematic. There would be no need for sophisticated timing recovery structures in this case.

Timing interpolator 416 generates a complex signal baseband which is processed by the output stage 406. The output stage includes an equalizer 420 and a decoder, carrier loop, or other equipment 422 that may utilize the data provided. The equalizer receives the complex signal from the timing interpolator and compensates for, or equalizes, the channel response. Such a filter may minimize the intersymbol interference. The modem such as seen at 30 or 28 may include, for example, a decoder, or slicer, that estimates the symbol sequence inherent in the transmitted signal. Such data may then be provided, for example, to the associated computer 24 or 26. The Timing Recovery Control 418 can be understood by first considering a perfect channel, where the transmit waveform arrives at the receiver undistorted. Consider the following sequence of transmitter symbols: "CCCCCCCCCCACACAAAAAAAAA", chosen for the purpose of illustration. It is a possible sequence, although it might not agree with one's intuitive concept of "random".

The envelope derived timing system takes the real and imaginary components of the receive waveform, which is of course sampled at a minimum of twice the symbol rate, and adds together the square of the x (real) component and the square of the y (imaginary) component. Consider the time domain behavior of the Timing Envelope ("TE") during the transmitter sequence above: The timing envelope will stabilize at a Direct Current ("DC") level during the period of "CCCCCCCC" or "AAAAAAAA", or any repeated symbol. The period of "ACACAC" will produce a sinusoid at the symbol rate for the duration of the pattern. This sinusoid contains the frequency and phase information necessary to recovery timing.

From this simple illustration, it can be seen that the timing information is data dependent. Consider the behavior of the timing envelope in the frequency domain. The "CCCCCCCCC" and "AAAAAAAA" patterns produce terms at 0 Hz. (in the transmitter baseband), and the "ACACACAC" pattern produces two tones, at (+/-) Fb/2, where Fb is the symbol rate. The receiver recovers timing information by intermodulating these two tones. This process produces a tone at frequency equal to the difference in the frequencies of the two tones. If the transmitted data pattern is viewed as a series of bursts of alternating patterns interspersed with bursts of repeated symbols, a certain portion of the total transmitter energy is in the regions known as the upper and lower bandedges, at Fb/2 and -Fb/2, respectively, of the data signal. This term is used because the bandedges represent the maximum positive and negative discreet frequencies that can be generated by any valid repeating sequence of symbols.

This concept of timing can be generalized to any pattern and mapping scheme. Any data pattern that produces energy near one bandedge also produces energy near the other bandedge. If these two lobes of energy both survive through the transmission channel, including the transmitter's spectral shaping filter, they may contribute to the timing recovery process in the receiver.

Envelope derived timing as described above works well on channels with moderate amplitude and delay distortion, but may perform poorly when these channel impairments are severe. A preferred embodiment circumvents these problems in an efficient manner by allowing a data receiver's timing recovery system to perform well, even on severely impaired channels with a minimal increase in complexity.

Unlike the energy in the region of the upper and lower bandedges that is useful for recovering timing, the remainder of the energy is not useful for timing recovery, and in fact interferes with the process. This "midband" energy can be thought of as interference or noise from the point of view of the timing recovery system. This concept of a Signal to Signal+Noise Ratio (S/S+NR) can be associated with the timing system.

The effect of amplitude rolloff on the timing envelope's S/S+NR is easy to understand when viewed in the frequency domain. If the energy at (+/-) Fb/2 is severely rolled off, the timing envelope sees much less relative timing energy, and a lower S/S+NR.

Another common problem associated with a communications channel is differential delay distortion. Suppose, for purposes of illustration, that the transmit signal consisted of two sinusoids, one at the lower bandedge and one at the upper bandedge, and that they were turned on simultaneously. This is the signal that would be produced by a burst of "ACACAC" in the example above. Assume that the communications channel has different delay at the two bandedges. Applicants have noted that this delay difference is a more significant factor than the the relative phase of these bandedge components, as others may have assumed. The delay difference (in milliseconds) can represent many symbol intervals. The relative phase difference in these sinusoids can only be resolved to the range 0 to 360 degrees by phase measurement.

Importantly, Applicants have noted that, to achieve optimum timing recovery, it is useful to introduce compensation so that the delays of the lower and upper bandedges are the same at the input to the timing envelope detector.

As mentioned above in the Background of the Invention section, such time delay compensation was not necessary for older modem standards that avoided frequencies in the severely distorted regions of the transmission channel. The problem often appears, however, when the modem attempts to use all available signaling bandwidth to achieve the highest possible data rate.

Following the model described above, the timing envelope exists only when the lower bandedge energy and upper bandedge energy arrive simultaneously, and are intermodulated by the squaring process. Furthermore, this timing envelope is only valid when the simultaneous upper and lower bandedge tones are associated with the same burst of data in the transmitter. No valid indication of timing phase is learned by the receiver if, for example, upper sideband energy associated with one burst of transmitter data coincides with lower sideband energy from a previous burst. The envelope detector may produce a tone at the symbol rate, but the phase and frequency of this tone is incidental, and not in general related to the actual symbol rate. If the differential delay between +Fb/2 and -Fb/2 exceeds the length of a given burst of alternations, no valid timing information is produced by that event. The greater the differential delay between bandedges, the less likely that a bursts of alternations will contribute to timing content in the timing envelope. Therefore, the timing envelope's S/S+NR is reduced for a channel with differential delay distortion.

One embodiment of the equalized envelope derived timing system of the present invention is shown in FIG. 5. Again, this approach is selected for illustration purposes, and there are many ways in which the embodiment shown in FIG. 5 may be implemented.

The embodiment shown in FIG. 5 explicitly compensates for differential delay distortion at the upper and lower bandedges. This embodiment also advantageously compensates for the effects of amplitude distortion on the communications channel.

The signal entering the Timing Interpolation Filter 504 is preferably sampled at a rate of 3 samples per symbol, and the center frequency of this signal is approximately 0. Timing Filter 504 generates an output signal at 2 samples per symbol, with no change in center frequency. These samples are placed in the equalizer delay line 506 where they are used for two purposes: as samples for the adaptive equalizer, which is part of the receiver's data recovery path, and also as samples for the Upper Band Edge Filter (UBEF) 508 and Lower Band Edge Filter (LBEF) 512, which are part of the Envelope Derived Timing Recovery system. The UBEF and LBEF can use different sets of samples from the delay line 506. A preferred embodiment uses 9 samples for the LBEF and 9 samples for the UBEF. For illustration purposes, assume that it has been determined that the the communications channel is delaying the lower bandedge energy more than the upper bandedge by 12 sample intervals. The LBEF could be configured to use the most recent samples, which could be labelled x(0)-x(8), and the UBEF will be configured to use the set of samples x(12)-x(20). (The larger index for xo indicates older, or more delayed, samples). In this manner, the delay in the upper bandedge path may be built out to be equal to the delay in the lower bandedge path. The samples used by the LBEF and UBEF are determined by the inputs T1 and Tu, respectively, which are generated in a manner to be explained.

The complex outputs of the UBEF and LBEF are summed together at the complex summing node 514, and this complex sum is processed by the Complex Squaring Function module 516 to produce the Timing Envelope which is an input to Band Pass filter (BPF) 518. BPF 518 passes energy at the symbol rate, and removes components near D.C. The output of the BPF 518 is processed by the Phase Comparator (PC) 520 which compares the phase of the BPF output to the local timing reference to produce an error term. The output of the PC block 520 is generated at the receive symbol rate.

The error term produced by PC 520 is accumulated over many symbol intervals to advantageously remove the effects of noise and interference from data patterns that do not contain valid timing information. This accumulation is performed by the Integrate and Dump (I and D) block 522. The output of this I and D block is generated at a reduced sample rate. This reduced rate is determined by the integration period of the I and D block, which is preferably 128 symbol periods.

The output of the I and D block is next processed by the Slicer block 524, which performs a SGN function, which generates a +1 or -1 depending on the sign of the input value.

The output of the Slicer is next processed by the PLL Loop Filter (PLL-LF) 526. PLL-LF is advantageously designed to predict the best sample phase and frequency for the Timing Interpolator Filter 504. The output of the PLL-LF is generated at the receive symbol rate and is added to the Timing Accumulator (TA) 528.

The TA 528 takes the predictor information from the PLL-LF, and decides when to begin processing the next batch of receive samples in the Timing Interpolator Filter (TIF) 504, and what timing offset should be used to generate the Interpolator Coefficients that will be used by the TIF. The Number of Samples per Baud (NSPB) output is nominally 3, but can be adjusted +/-1 to accomodate an overspeed or underspeed scenario. TA 528 generates a Timing Interpolator Parameter (TIP) output for the Coefficient Computation (CC) block 530. The Coefficient Computation (CC) block 530 converts the TIP to a set of filter interpolation coefficients with the desired delay characteristics for use by TIF 504.

Amplitude Distortion Compensation

The upper bandedge filter 508 passes energy in a region centered at the upper bandedge, and the lower bandedge filter 512 passes energy in a region centered at the lower bandedge. The rest of the energy which includes all the energy in the center of the band, contains no timing information, and is sharply attenuated by the upper and lower bandedge filters. This has the effect of improving the timing envelope S/S+NR on all channels, but the effect is most dramatic when the channel is severely rolled off at one or both bandedges.

This filtering technique is superior to simple amplitude equalization of the channel prior to extraction of the timing envelope, because equalization boosts the desired energy at the bandedges, but also boosts the unwanted energy near the bandedges.

Delay Distortion Compensation

The group delay at the upper and lower bandedges are defined as Du and D1, respectively. Let Dd=Du-D1, the differential delay between upper and lower bandedges. Assume that Dd can be estimated accurately. Let Dc=compensation delay=-Dd. Then, the two parameters Tu and T1 can be established such that Tu-T1=Dc.

Furthermore, set either T1=0 or Tu=0, depending on the sign of Dc. If Dc is negative, Tu=0, and T1=-Dc. Alternatively, if Dc is positive, T1=0, and Tu=Dc.

Thus, the parameters Tu and T1 are advantageously used to introduce delay into either the upper or lower bandedge filter. The difference in delay in these filters is opposite in sign to the differential delay imposed by the channel. Therefore, the channel delay is equalized in the region that contains timing energy. This compensation is achieved with a single degree of freedom, Dc. This parameter can preferably be estimated at the beginning of modem training, for example, and fixed during data transmission.

This Delay line 506 is part of the modem receiver's adaptive equalizer, which is implemented as an adaptive Finite Impulse Response (FIR) filter. The samples in this delay line are also used as the sample set for the bandedge filter, which is preferably implemented as a fixed coefficient FIR filter. If it is desired to introduce a delay of N symbols in the upper bandedge filter, and the filter has K coefficients, then the most recent 2N samples are skipped, and the next K samples starting at sample 2N, are processed. The equalizer delay line 506 is of finite length, but long enough for the desired compensation. This is because, if the delay line is long enough to compensate for amplitude and delay distortion in general, it is long enough to compensate for the differential delay distortion at a particular pair of frequencies.

The estimation of parameters Tu and T1 can be accomplished by a number of means. In a preferred embodiment, the parameters Tu and T1 are initialized to a compromise value for initial receiver training. The receiver's adaptive equalizer is trained initially with this compromise value for timing compensation. This value for timing compensation will not be optimum for many channels of interest, but this primarily effects long term stability of the receiver, and does not significantly effect the short term convergence of the equalizer.

At a convenient point in the training sequence, the equalizer coefficients are analyzed. The delay distortion is computed at a point near the upper bandedge, and a corresponding point near the lower bandedge. The two delays are subtracted to produce the desired result, Dc. Tu and T1 are then determined as discussed above. The bandedges are preferably not used because the adaptive equalizer can generate an ambiguous result at these particular frequencies.

Several alternative methods exist to determine the appropriate time delay to compensate for delay distortion, including compromise delay equalizer at input of the modem receiver. Also, the modem may simply conduct a test during a training, or handshake, sequence before any data is transmitted. During the training sequence, the bandedge delay for a known signal may be measured and then used for appropriate compensation during the later data transmission.

The input to the Timing Interpolator Filter 504 shown in FIG. 5 is a sequence of complex numbers -x(n)+j'y(n) (the time index n is understood). This frequency spectrum of this complex baseband signal is centered at 0, and has both positive and negative frequencies. The upper bandedge filter substantially passes only positive frequencies centered around +fb/2, and the lower bandedge filter only negative frequencies centered around -fb/2.

In order for a filter to discriminate between positive and negative frequencies, it must operate on complex numbers. These filters also must have complex coefficients. Hence the inputs are complex, the coefficients are complex, and the two outputs are complex.

The coefficients for the UBEF 508 and LBEF 512 are preferably generated by first designing a low pass prototype filter, and then modulating this prototype filter's coefficients by a complex sinusoid at +fb/2, and at -fb/2, which generates the two sets of coefficients desired, for the upper and lower bandedge filters. Although the foregoing description of the preferred embodiment will enable a person of ordinary skill in the art to make and use the invention, five detailed assembly language subroutine₋₋ listings are included below. The first listing subroutine, entitled "Estimate Differential Delay Compensation," estimates the differential delay distortion near the upper and lower bandedges, and generates the paramters Tu and T1, which determine what samples are used by the UBEF and LBEF.₋₋ The second listing, subroutine, entitled "Receiver Baud Timing Recovery System," implements TIF 504 management, UBEF/LBEF 508/512 management, complex summing node 514, Complex Squaring Function 516, BPF 518, and PC 520 functions.

The third listing, entitled "Baud Loop Filter," implements the Slicer 524, PLL-LF 526, TA 528 functions, and the UBEF/LBEF 508/512 filter functions. The code for managing the UBEFILBEF function is contained in the "Receiver Baud Timing Recovery System" listing described above.

The fourth listing, entitled "Update Baud Timing Parameter," decomposes the data from the Timing Accumulator into two parts: (1) NSPB, nominally 3, but adjusted by +1 or -1 depending depending on relative frequencies of local and remote symbol rate, and accumulated error, and (2) The Timing Interpolation Parameter which is used to generate the coefficients of the interpolator filters. This subroutine also generates the coefficients for this timing interpolator. The fifth listing, entitled "3:2 Timing Interpolator," computes the T/2 outputs for the Receive Equalizer Sample Delay Line 506 based on the interpolation coefficients. While the code for this interpolator function resides in "3:2 Timing Interpolator", it is under the control of code in the "Receiver Baud Timing Recovery System" described above. Each of the programs listed below may be converted into machine executable form using the `320C2/C5x Assembler available from the Texas Instruments Corporation. Additional detailed features of the system will become apparent to those skilled in the art from reviewing these programs. ##SPC1##

A preferred embodiment of the present invention has been described herein. It is to be understood, of course, that changes and modifications may be made in the embodiment without departing from the true scope and spirit of the present invention, as defined by the appended claims. 

We claim:
 1. In an electronic data receiver, an envelope derived timing system for receiving a modulated signal which contains encoded information containing energy at an upper bandedge and at a lower bandedge, comprising:a timing interpolator; and a timing loop interconnected to said timing interpolator, said timing loop including, a timing compensator for receiving said modulated signal and temporally adjusting said upper bandedge energy with respect to said lower bandedge energy to compensate for delay distortion of said modulated signal at said upper bandedge and said lower bandedge, and responsively providing time-compensated component signals, and a timing recovery system that processes said time-compensated component signals and responsively provides a phase control signal to said interpolator.
 2. A receiver for accepting a transmitted signal generated by a remote transmitter and responsively providing an equalized signal to a decoder, said receiver comprising, in combination:a demodulator for providing a complex baseband signal a timing interpolator for receiving said complex baseband signal from said demodulator and providing interpolated samples, in accordance with a phase control signal, at a rate synchronized in phase and frequency to symbol transitions in said transmitted signal, said interpolated samples being a complex signal having upper and lower bandedge components; a timing loop interconnected to said timing interpolator, said timing loop includinga timing compensator for receiving said interpolated samples and providing time compensated signals in accordance with a compensating delay, said compensating delay compensating for the differential delay between said upper and lower bandedge components, and a timing envelope sensor for receiving said time-compensated signals and responsively providing said phase control signal to said interpolator; and an equalizer for receiving said samples from said interpolator, reducing intersymbol interference, and providing an equalized signal to said decoder.
 3. A receiver as claimed in claim 2 further comprising an estimator for determining said differential delay between said upper and lower bandedge component signals and for generating said compensating delay.
 4. A receiver as claimed in claim 3 wherein said estimator includes training means for receiving a known signal over said communications channel and for measuring an actual time delay distortion based upon said received known signal to generate said compensating delay.
 5. A receiver as claimed in claim 4 wherein said equalizer includes an adaptive filter which generates a plurality of coefficients and said estimator selects said coefficients in accordance with said compensating delay.
 6. A method for recovering a timing envelope in an electronically transmitted signal comprising, in combination:splitting said transmitted signal into a complex signal; generating a delay measurement indicative of the relative delay between upper and lower bandedge components of said complex signal; compensating for delay distortion between said upper and lower bandedge components in response to said delay measurement and responsively determining a synchronization rate: separating said complex signal into samples at said synchronization rate; equalizing said samples; and decoding said samples into data.
 7. A method as claimed in claim 6 wherein said transmitted signal defines a symbol rate and at least first and second frequencies corresponding to said synchronization rate and wherein said method further comprises filtering said complex signal to obtain first and second frequency signals and utilizing said first and second frequency signals to determine said synchronization rate.
 8. A method as claimed in claim 6 wherein the step of generating a delay measurement comprises the step of receiving a known signal, measuring an actual time delay distortion based upon said received known signal, and generating said delay measurement as a function of said actual time delay distortion.
 9. A symbol timing control apparatus comprising:a sample delay line; a timing filter connected to said sample delay line, said timing filter having an upper bandedge filter and a lower bandedge filter, said timing filter adapted to adjust the relative phase between said upper bandedge filter and said lower bandedge filters in response to a delay estimation signal; an estimator connected to said timing filter to provide said delay estimation signal; and a timing recovery system responsive to said timing signal for generating a timing error signal.
 10. The apparatus of claim 9 further comprising an interpolation filter connected to said sample delay line, said interpolation filter outputting said first sampled data sequence to said sample delay line, wherein said first sampled data sequence is generated from a second sampled data sequence in response to said timing error signal.
 11. The apparatus of claim 9 wherein said timing filter is a finite impulse response filter.
 12. The apparatus of claim 9 further comprising an equalizer coupled to said sample delay line.
 13. A receiver as claimed in claim 12 wherein said equalizer includes equalizer coefficients and said estimator determines said delay estimation signal in response to said equalizer coefficients.
 14. The apparatus of claim 9 wherein said upper bandedge filter and said lower bandedge filter accept inputs from said sample delay line at positions determined by said estimator.
 15. The apparatus of claim 3 wherein said equalizer includes equalizer coefficients and said estimator determines said compensating delay in response to said equalizer coefficients.
 16. A timing recovery apparatus comprising:an interpolation filter having interpolation coefficients; a tap delay line connected to said interpolation filter; a delay estimator; a timing filter connected to said tap delay line and said delay estimator, said timing filter having an upper bandedge filter and a lower bandedge filter, wherein the relative phase response between said upper and lower bandedge filters is determined in response to said delay estimator; a squaring device connected to said timing filter; a phase comparator connected to said squaring device, wherein said interpolation coefficients are adjusted in response to said phase comparator. 